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Description
The increasing data production rates at accelerator-based light sources necessitate the development and adoption of efficient data reduction and compression techniques [1]. Pre-storage data reduction, as well as various forms of on-the-fly processing systems [2], are becoming increasingly prevalent. Hardware-accelerated computing, particularly heterogeneous GPU–CPU–FPGA systems [2], offers an energy-efficient and sustainable infrastructure for the automated processing of photon science data. Typical applications include spot finding, indexing of diffraction patterns, tomographic reconstruction, small-angle scattering simulations, and azimuthal integration (AZINT).
This contribution focuses primarily on the latter application, AZINT, implemented on FPGAs several years ago [3]. The work explores an efficient end-to-end implementation of all processing stages, including data decompression, on a single FPGA device, with an emphasis on optimizing memory access patterns and bandwidth utilization.
Experimental data are often delivered already compressed by detectors to reduce network bandwidth requirements or stored in compressed form for practical reasons. We present the challenges associated with implementing the bitshuffle-LZ4 decompression method on FPGA hardware and compare it with alternative LZ77-based approaches, particularly Snappy compression. This comparison highlights how the selection of a compression scheme, often guided by performance on general-purpose computing architectures, can significantly impact its efficiency when implemented in dedicated hardware.
[1] N. Soler, V. Favre-Nicolin, LEAPS-INNOV D7.1 - Evaluation report on data rates & volumes and assessment of future needs of LEAPS facilities, doi:10.5281/zenodo.17099463
[2] F. Leonarski et al., J. Synchrotron Radiat., 30, (2023), 227. doi:10.1107/S1600577522010268
[3] Z. Matěj et al., bincount implementation of Azimuthal Integration (AZINT) with FPGAs, gitlab.com/MAXIV-SCISW/compute-fpgas/bincount
